1. Field of the Invention
The present invention relates to a semiconductor storage unit having redundant memory cells. In particular, the invention relates to a semiconductor storage unit capable of reducing the size of a chip thereof.
2. Description of the Prior Art
In general, a redundant memory cell selection decoder having fuses is used in semiconductor storage units having redundant memory cells. In such semiconductor storage units, the number of necessary fuses in the redundant memory cell selection decoder increases as the memory capacity increases. However, it is more difficult to miniaturize such semiconductor storage units than other circuit elements because the fuses need to be cut by laser light application, for example.
For example, in the redundant memory cell selection decoder that is described as a prior art technique in Japanese Patent Laid-Open No. 5-28794, a block selection signal is used as an input of the redundant memory cell decoder. In this technique, since one complementary fuse is necessary for each address signal, the number of fuses necessary for a 3-bit address is 3xc3x972=6.
In view of the above, a column redundant circuit for a semiconductor memory device has been proposed to reduce the number of fuses (Japanese Patent Laid-Open No. 8-77791). In the conventional column redundant circuit disclosed in this publication, nine fuses including a master fuse are provided for an 8-bit column address.
However, although the conventional column redundant circuit disclosed in Japanese Patent Laid-Open No. 8-77791 can reduce the number of fuses, other circuits are complex in configuration and hence the chip size miniaturization is insufficient.
The present invention has been made to solve the above problems in the art, and an object of the invention is therefore to provide a semiconductor storage unit which can reduce the number of fuses and the size of a chip.
The invention provides a semiconductor storage unit comprising a memory cell array that is sectioned into a plurality of blocks; a redundant memory cell; and a redundant memory cell selection circuit for replacing a defective memory cell in the memory cell array with the redundant memory cell in such a manner that the replacement is correlated with a first block selection signal for selecting a prescribed block from among the plurality of blocks and a second block selection signal that is reverse in logical value to the first block selection signal.
In the invention, the redundant memory cell selection circuit replaces a defective memory cell in the memory cell array with the redundant memory cell in such a manner that the replacement is correlated with the first block selection signal and the second block selection signal that is reverse in logical value to the first block selection signal. Therefore, the number of fuses for determining the address of a defective memory cell can be reduced and the circuit configuration for that purpose can be simplified. As a result, the chip size can be reduced.
The redundant memory cell selection circuit may comprise first field-effect transistors to whose gates the first block selection signal is input; second field-effect transistors to whose gates the second block selection signal is input and that are different in channel conductivity type from the first field-effect transistors; and fuses connected between the sources or drains of the first field-effect transistors and those of the second field-effect transistors, respectively.
Further, the memory cell array may be sectioned into a plurality of column or row blocks.
Further, a plurality of redundant memory cells that configure a redundant memory cell block may be provided as the redundant memory cell.
Further, the first field-effect transistors and the second field-effect transistors may be provided by one per one bit of a memory cell address.